Chip Startup XCENA Aims to Revolutionize AI Infrastructure

Every time you ask ChatGPT a question, your request triggers a data relay race. Information leaves memory, passes through a CPU for preprocessing, travels to a GPU for heavy computation, and then makes its way back — and that entire journey repeats for every single word the AI generates. This bottleneck is structural — it means routing through some of the most expensive and power-intensive chips in the industry on every single request.

The four-year-old startup XCENA, with offices in South Korea and the U.S., is trying to solve this issue. They have designed a chip that places compute capabilities much closer to DRAM — the fast, short-term memory chips that store data a processor is actively using — allowing routine data operations to be handled near memory, without the costly round trips between CPUs, GPUs, and memory.

XCENA CEO Jin Kim co-founded the startup in 2022 alongside CTO Dohun Kim and CPO Harry Juhyun Kim, all veterans of Samsung and SK Hynix, the memory giants that supply chips powering Nvidia's GPUs.

"CPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that," Kim said in an interview with TechCrunch. "The recent rise in memory prices and related stocks points to a broader shift in AI infrastructure toward memory-centric architectures," he added.

XCENA is betting its business on the thesis that "inference isn't just a compute problem; it's increasingly a memory scaling problem," said Kim.

XCENA's chip, the MX1, connects to the CPU through CXL (Compute Express Link) — essentially a dedicated express lane between the processor and memory — processing data before it ever needs to leave the memory module. It brings compute to the data, not the other way around. The company claims that what used to require 10 servers could potentially run on just one.

While GPUs excel at matrix multiplication — the heavy math behind AI model training — much of the surrounding data orchestration, including preprocessing, KV cache management, and data caching, still runs on CPUs. Our chip handles those tasks directly within the memory module itself," Kim said.

The company believes the timing is working in its favor, as demand for memory solutions has surged since the second half of last year. XCENA is in early-stage conversations with several global memory vendors, though Kim declined to name them. The company's ideal customers are hyperscalers spending tens of billions a year on AI infrastructure, where even a small gain in memory efficiency can mean hundreds of millions in savings.

The MX1 is still a prototype, but mass production chips are scheduled to roll off Samsung's foundry lines by the end of 2026, with the company expecting to generate revenue starting in 2027. While neural processing unit (NPU) makers are competing to challenge Nvidia for training workloads, XCENA is targeting the memory-intensive layer that sits underneath all of it.

XCENA's closest rivals include Astera Labs and Marvell, both Nasdaq-listed companies working on next-generation memory connectivity. Marvell is a large, established player already working in the same space, Kim said, adding that the differentiator comes down to intellectual property. "We have thousands of cores," Kim said. Based on public specs, Marvell's approach relies on a handful of general-purpose cores by comparison.

XCENA designs its own internal memory hierarchy, interconnect bus, and DRAM controller — a level of vertical integration that most chip companies, including larger rivals, typically outsource. The company has more than 90 staff across offices in Pangyo, a tech hub outside Seoul, and in Sunnyvale.

Seoul-based VC firms Altinum and IMM Investment co-led the Series B round, along with Corstone Asia and existing investors SBI Investment and Mirae Asset Capital. The company is also in conversations with international investors about additional funding.